1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly relates to a structure of a non-volatile memory referred to as a split gate type non-volatile semiconductor memory device, and a manufacturing method the same
2. Description of the Related Art
As a non-volatile semiconductor memory device in which a storage content is not erased even if a power source is turned off, a split gate type non-volatile semiconductor memory device is known (for example, refer to U.S. Pat. No. 6,525,371B2 and Japanese Laid Open Patent Application (JP-P2004-200181A)). In recent years, a larger capacity of the non-volatile semiconductor memory device is strongly requested, and for this reason, it is essential to apply a finer pattern process to a memory element. Also, the smaller power consumption is strongly requested. For this reason, it is necessary to perform a write operation at a low voltage, an erasing operation at a low voltage and a read operation at a low current. In order to meet those requests, the respective electric characteristics of the plurality of memory elements are required to be uniform. For this purpose, the respective shapes of the memory elements are required to be configured uniformly and stably.
FIG. 1 is a sectional view showing the configuration of the split gate type non-volatile semiconductor memory device described in the U.S. Pat. No. 6,525,371B2 as a first conventional example). A non-volatile memory device 101 in the first conventional example has source diffusion layers 103 and drain diffusion layers 104. With reference to FIG. 1, the source diffusion layers 103 and the drain diffusion layers 104 are formed on a semiconductor substrate 102. As shown in FIG. 1, the split gate type non-volatile memory device 101 has floating gates 105 and control gates 106. The floating gate 105 is formed through a gate oxide film 107 on the substrate 102. Also, the control gate 106 is formed through a tunnel oxide film 108 on the substrate 102. Also, the tunnel oxide film 108 is formed between the floating gate 105 and the control gate 106.
Operations of the split gate type non-volatile memory device 101 in the first conventional example will be described below. FIGS. 2A to 2C are diagram showing the operations of the conventional split gate type non-volatile memory device 101. FIG. 2A shows a writing operation, FIG. 2B shows an erasing operation, and FIG. 2C shows a reading operation, in the split gate type non-volatile memory device 101. With reference to FIG. 2A, when a data is written to the split gate type non-volatile memory device 101, a voltage of the source diffusion layer 104 is set to be higher than that of the drain diffusion layer 103. Thus, hot electrons (electrons in a high energy state) are generated on a source side of a channel. The hot electrons are injected through the gate oxide film 107 into the floating gate 105, and thereby, the data is written. After the data is written, the floating gate becomes in a negatively electrified state.
With reference to FIG. 2B, when the data stored in the split gate type non-volatile memory device 101 is erased, the electrons are pulled out from the floating gate 105 to the control gate 106 through the tunnel oxide film 108 as a tunnel current, and the data is erased. In short, at the time of the erasure, a voltage is applied to the control gate 106, and a electric field is concentrated on a sharpened portion (an acute angle portion 110) of a tip portion of the floating gate 105, and the electrons are pulled out from the floating gate 105. After the erasure, the floating gate is in the positively electrified state.
With reference to FIG. 2C, when the data is read out from the split gate type non-volatile memory device 101, a predetermined voltage is applied to the control gate 106, and a transistor of the control gate 106, the source diffusion layer 103 and the drain diffusion layer 104 is activated. At this time, in response to the charges having injected in the floating gate 105, a value of the current flowing between the source diffusion layer 104 and the drain diffusion layer 103 is changed, thereby reading the data.
In this way, in the split gate type non-volatile memory device 101 having such a structure, the acute angle portion 110 of the floating gate 105 is required to be formed stably at a high precision. The technique for forming the acute angle portion 110 at the high precision is known, for example, in Japanese Laid Open Patent Application (JP-P2004-200181A: a second conventional example).
A method of manufacturing the split gate type non-volatile memory device 101 in the second conventional example will be described below. FIGS. 3A to 31 are cross sectional views showing the method of manufacturing the split gate type non-volatile memory device 101 in the second conventional example.
With reference to FIG. 3A, a gate oxide film 111 of 8 nm, a polysilicon film 112 of 80 nm and a silicon nitride film 113 of 300 nm are sequentially formed on the silicon substrate 102. Then, a photo resist layer 124 is formed on the silicon nitride film 113 as a pattern of floating gate and source formation regions.
Next, with reference to FIG. 3B, the silicon nitride film 113 is dry-etched by using the photo resist layer 124 as a mask, so that an opening is formed. Then, the resist is ashed.
Next, with reference to FIG. 3C, the opening of the silicon nitride film 113 is used as mask, and the polysilicon film 112 is etched to the depth of about 30 nm. Thus, a tapered portion having the angle of 45 degrees is generated.
Next, with reference to FIG. 3D, a thermal oxide film 114 of about 6 nm is formed at 850° C. on the surface of the polysilicon film 112.
Next, with reference to FIG. 3E, an LPCVD method is used to form a TEOS-NSG film of about 20 nm on the entire surface. Subsequently, when the TEOS-NSG film is etched by a dry etching apparatus of a RIE type, an NSG spacer 120 is formed to an extent that the tapered portion of the polysilicon film 112 is just concealed.
Next, with reference to FIG. 3F, an annealing process of about 850° C. is performed to anneal the TEOS-NSG film. Subsequently, an NSG film of about 160 nm is formed by the LPCVD method and then etched. Thus, an NSG spacer 115 is formed.
Next, with reference to FIG. 3G, an NSG spacer 116, a source diffusion region 117, a polysilicon plug 118 and a thermal oxide film 119 are formed. Subsequently, the silicon nitride film 113 is removed, for example, by using H3PO4 of 150° C.
Next, with reference to FIG. 3H, the NSG spacer 115, the NSG spacer 120 and the thermal oxide film 119 are used as masks, to dry-etch the polysilicon film 112. At this time, the acute angle portion 110 is formed.
Next, with reference to FIG. 31, the NSG spacer 120 is removed, for example, by wet-etching of 5% fluorine acid for 40 seconds. Thus, the sharpened portion of the acute angle portion 110 is formed.
In the first and second conventional examples, cross sectional views are shown in which the acute angle portion 110 is formed. In this case, since the height of the control gate is defined on the basis of the height of the silicon nitride film 113, the silicon nitride film would be required to have the thickness of about 300 nm. It is technically very difficult to perform the dry etching on the thick silicon nitride film 113 stably and vertically to the substrate. FIGS. 4A to 4D are cross sectional views showing the manufacturing steps when the silicon nitride film 113 is not etched vertically to the substrate.
With reference to FIG. 4A, as mentioned above, the gate oxide film 111 of 8 nm, the polysilicon film 112 of 80 nm and the silicon nitride film 113 of 300 nm are sequentially formed on the silicon substrate 102. Then, the photo resist layer 124 is formed on the silicon nitride film 113 to have a pattern of the floating gate and source formation regions. Here, the resist mask 124 is formed at an interval of a first distance L1. The first distance L1 is a length corresponding to the floating gate length of the split gate type non-volatile memory device 101 that is desired to be finally formed.
Next, with reference to FIG. 4B, the photo resist layer 124 is used as a mask, and the silicon nitride film 113 is dry-etched to form an opening. Then, the resist is ashed. At this time, there is a case that the side wall of the silicon nitride film 113 that is formed through the etching is not formed in parallel to the normal line to the substrate 102 surface. At this time, the length of the exposed surface of the polysilicon film 112 would be become a second distance L2.
Next, with reference to FIG. 4C, the NSG spacer 115, the NSG spacer 120 and the thermal oxide film 119 are used as a mask, and the polysilicon film 112 is dry-etched. As a result, the floating gate having the acute angle portion 110 is formed. In this case, when the side wall of the opening of the silicon nitride film 113 is inclined, there is a case that correspondingly to the inclination, the side wall of the NSG spacer 120 is also inclined outside the NSG spacer 120. Thus, there is a case that the etching is performed at a fourth distance L4 from the end of the floating gate 105 on the drain side so that a step 112 of the polysilicon film is formed.
Next, with reference to FIG. 4D, through the above steps, the acute angle portion 110 is improperly formed in the split gate type non-volatile memory device 101. As mentioned above, the silicon nitride film 113 is required to be formed at the thickness of about 300 nm. In this case, it is technically very difficult to stably etch the silicon nitride film 113 vertically to the substrate surface. For example, there is a case that reactive product at the time of the etching is deposited on the nitride film side, which disturbs the etching. In this case, as the etching is advanced to a lower portion, the wall of the opening is inclined to a direction that the opening width becomes narrower. Thus, when the conventional technique is used to form the floating gate 105 having the acute angle portion 110, there is a case that because of the variation in the inclination angle of the silicon nitride film 113, the actual acute angle portion 110 cannot be formed in the ideal shape.
As mentioned above, in the conventional split gate type non-volatile memory, the charges stored in the floating gate 105 are pulled out through the acute angle portion 110 into the control gate 106, and the data is consequently erased. When the acute angle portion 110 of the floating gate 105 is properly formed, the electric field can be concentrated on the acute angle portion 110. Thus, the electrons can be properly pulled out from the floating gate 105. However, when the side wall of the opening of the silicon nitride film 113 is inclined, there is a case that the actual acute angle portion 110 cannot be formed in the ideal shape. If the variation in the shape of the acute angle portion 110 is larger, the variation in the erasure property becomes also greater. As a result, the normal and stable operation of the split gate type non-volatile memory cannot be achieved.